On 06/11/2016 09:10 PM, Bjorn Helgaas wrote:
> On Mon, May 09, 2016 at 01:48:27PM +0200, Niklas Cassel wrote:
>> From: Niklas Cassel
>>
>> This commit adds the Device Tree binding documentation that allows to
>> describe the PCIe controller found in the Axis ARTPEC-6 SoC.
>>
>> Signed-off-by: Nik
On Mon, May 09, 2016 at 01:48:27PM +0200, Niklas Cassel wrote:
> From: Niklas Cassel
>
> This commit adds the Device Tree binding documentation that allows to
> describe the PCIe controller found in the Axis ARTPEC-6 SoC.
>
> Signed-off-by: Niklas Cassel
I applied both of these, with Rob's ack
On Mon, May 09, 2016 at 01:48:27PM +0200, Niklas Cassel wrote:
> From: Niklas Cassel
>
> This commit adds the Device Tree binding documentation that allows to
> describe the PCIe controller found in the Axis ARTPEC-6 SoC.
>
> Signed-off-by: Niklas Cassel
> ---
> Changes since v1:
> - Rename sy
From: Niklas Cassel
This commit adds the Device Tree binding documentation that allows to
describe the PCIe controller found in the Axis ARTPEC-6 SoC.
Signed-off-by: Niklas Cassel
---
Changes since v1:
- Rename syscon node to be more descriptive
.../devicetree/bindings/pci/axis,artpec6-pcie.
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