Hello Mark,
On 2019/09/03 20:11, Mark Brown wrote:
On Tue, Sep 03, 2019 at 04:19:10AM +0900, Katsuhiro Suzuki wrote:
On 2019/09/02 21:02, Mark Brown wrote:
The best way to handle this is to try to support both fixed and variable
clock rates, some other drivers do this by setting constraints
On Tue, Sep 03, 2019 at 04:19:10AM +0900, Katsuhiro Suzuki wrote:
> On 2019/09/02 21:02, Mark Brown wrote:
> > The best way to handle this is to try to support both fixed and variable
> > clock rates, some other drivers do this by setting constraints based on
> > MCLK only if the MCLK has been set
Hello Mark,
Thanks a lot for your comments.
On 2019/09/02 21:02, Mark Brown wrote:
On Sun, Sep 01, 2019 at 01:26:48AM +0900, Katsuhiro Suzuki wrote:
This patch change the judge timing about playing/capturing PCM rate.
Original code set constraints list of PCM rate limits at set_sysclk.
This s
On Sun, Sep 01, 2019 at 01:26:48AM +0900, Katsuhiro Suzuki wrote:
> This patch change the judge timing about playing/capturing PCM rate.
>
> Original code set constraints list of PCM rate limits at set_sysclk.
> This strategy works well if system is using fixed rate clock.
>
> But some boards and
This patch change the judge timing about playing/capturing PCM rate.
Original code set constraints list of PCM rate limits at set_sysclk.
This strategy works well if system is using fixed rate clock.
But some boards and SoC (such as RockPro64 and RockChip I2S) has
connected SoC MCLK out to ES8316
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