Re: [PATCH v2 1/3] dt-bindings: Document JZ47xx VPU auxiliary processor

2019-08-21 Thread Paul Cercueil
Hi Rob, Le mar. 20 août 2019 à 22:50, Rob Herring a écrit : On Mon, Jul 29, 2019 at 02:31:07PM -0400, Paul Cercueil wrote: Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from Ingenic is a second Xburst MIPS CPU very similar to the main core. This document describes the

Re: [PATCH v2 1/3] dt-bindings: Document JZ47xx VPU auxiliary processor

2019-08-20 Thread Rob Herring
On Mon, Jul 29, 2019 at 02:31:07PM -0400, Paul Cercueil wrote: > Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from > Ingenic is a second Xburst MIPS CPU very similar to the main core. > This document describes the devicetree bindings for this auxiliary > processor. > >

[PATCH v2 1/3] dt-bindings: Document JZ47xx VPU auxiliary processor

2019-07-29 Thread Paul Cercueil
Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from Ingenic is a second Xburst MIPS CPU very similar to the main core. This document describes the devicetree bindings for this auxiliary processor. Signed-off-by: Paul Cercueil --- Notes: v2: Update TCSM0 address in example