Hi Rob,
Le mar. 20 août 2019 à 22:50, Rob Herring a écrit :
On Mon, Jul 29, 2019 at 02:31:07PM -0400, Paul Cercueil wrote:
Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs
from
Ingenic is a second Xburst MIPS CPU very similar to the main core.
This document describes the
On Mon, Jul 29, 2019 at 02:31:07PM -0400, Paul Cercueil wrote:
> Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
> Ingenic is a second Xburst MIPS CPU very similar to the main core.
> This document describes the devicetree bindings for this auxiliary
> processor.
>
>
Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
Ingenic is a second Xburst MIPS CPU very similar to the main core.
This document describes the devicetree bindings for this auxiliary
processor.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Update TCSM0 address in example
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