On 12/05/2014 06:41 AM, rajeev kumar wrote:
> On Wed, Dec 3, 2014 at 6:05 PM, Harini Katakam wrote:
>> The I2C controller sends a NACK to the slave when transfer size register
>> reaches zero, irrespective of the hold bit. So, in order to handle transfers
>> greater than 252 bytes, the transfer si
Hi,
On Fri, Dec 5, 2014 at 11:11 AM, rajeev kumar
wrote:
> On Wed, Dec 3, 2014 at 6:05 PM, Harini Katakam wrote:
>> The I2C controller sends a NACK to the slave when transfer size register
>> reaches zero, irrespective of the hold bit. So, in order to handle transfers
>> greater than 252 bytes,
On Wed, Dec 3, 2014 at 6:05 PM, Harini Katakam wrote:
> The I2C controller sends a NACK to the slave when transfer size register
> reaches zero, irrespective of the hold bit. So, in order to handle transfers
> greater than 252 bytes, the transfer size register has to be maintained at a
> value >=
Hi,
On Fri, Dec 5, 2014 at 12:02 AM, Wolfram Sang wrote:
>
>> + /*
>> + * If the device is sending data If there is further
>> + * data to be sent. Calculate the available space
>> + * in FIFO and fill the FIFO with that many bytes.
>> +
> + /*
> + * If the device is sending data If there is further
> + * data to be sent. Calculate the available space
> + * in FIFO and fill the FIFO with that many bytes.
> + */
This comment looks broken. In general, I think there sho
The I2C controller sends a NACK to the slave when transfer size register
reaches zero, irrespective of the hold bit. So, in order to handle transfers
greater than 252 bytes, the transfer size register has to be maintained at a
value >= 1. This patch implements the same.
The interrupt status is clea
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