Re: [PATCH v2 1/3] i3c: fix i2c and i3c scl rate by bus mode

2019-06-06 Thread Boris Brezillon
On Thu, 6 Jun 2019 18:08:11 + Vitor Soares wrote: > From: Boris Brezillon > Date: Thu, Jun 06, 2019 at 18:35:40 > > > On Thu, 6 Jun 2019 17:16:55 + > > Vitor Soares wrote: > > > > > From: Boris Brezillon > > > Date: Thu, Jun 06, 2019 at 15:18:44 > > > > > > > On Thu, 6 Jun 2019

RE: [PATCH v2 1/3] i3c: fix i2c and i3c scl rate by bus mode

2019-06-06 Thread Vitor Soares
From: Boris Brezillon Date: Thu, Jun 06, 2019 at 18:35:40 > On Thu, 6 Jun 2019 17:16:55 + > Vitor Soares wrote: > > > From: Boris Brezillon > > Date: Thu, Jun 06, 2019 at 15:18:44 > > > > > On Thu, 6 Jun 2019 16:00:01 +0200 > > > Vitor Soares wrote: > > > > > > > Currently the I3C fr

Re: [PATCH v2 1/3] i3c: fix i2c and i3c scl rate by bus mode

2019-06-06 Thread Boris Brezillon
On Thu, 6 Jun 2019 17:16:55 + Vitor Soares wrote: > From: Boris Brezillon > Date: Thu, Jun 06, 2019 at 15:18:44 > > > On Thu, 6 Jun 2019 16:00:01 +0200 > > Vitor Soares wrote: > > > > > Currently the I3C framework limits SCL frequency to FM speed when > > > dealing with a mixed slow bu

RE: [PATCH v2 1/3] i3c: fix i2c and i3c scl rate by bus mode

2019-06-06 Thread Vitor Soares
From: Boris Brezillon Date: Thu, Jun 06, 2019 at 15:18:44 > On Thu, 6 Jun 2019 16:00:01 +0200 > Vitor Soares wrote: > > > Currently the I3C framework limits SCL frequency to FM speed when > > dealing with a mixed slow bus, even if all I2C devices are FM+ capable. > > > > The core was also not

Re: [PATCH v2 1/3] i3c: fix i2c and i3c scl rate by bus mode

2019-06-06 Thread Boris Brezillon
On Thu, 6 Jun 2019 16:00:01 +0200 Vitor Soares wrote: > Currently the I3C framework limits SCL frequency to FM speed when > dealing with a mixed slow bus, even if all I2C devices are FM+ capable. > > The core was also not accounting for I3C speed limitations when > operating in mixed slow mode

[PATCH v2 1/3] i3c: fix i2c and i3c scl rate by bus mode

2019-06-06 Thread Vitor Soares
Currently the I3C framework limits SCL frequency to FM speed when dealing with a mixed slow bus, even if all I2C devices are FM+ capable. The core was also not accounting for I3C speed limitations when operating in mixed slow mode and was erroneously using FM+ speed as the max I2C speed when opera