On 10/20/2018 12:49 PM, Andy Shevchenko wrote:
> On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
>> From: Javier Arteaga
>>
>> UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
>> features a MAX 10 FPGA that routes lines from both SoC and on-board
>> devices to two
On 10/20/2018 12:49 PM, Andy Shevchenko wrote:
> On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
>> From: Javier Arteaga
>>
>> UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
>> features a MAX 10 FPGA that routes lines from both SoC and on-board
>> devices to two
On Thu, Oct 25, 2018 at 12:05:05PM +0100, Lee Jones wrote:
> On Sat, 20 Oct 2018, Andy Shevchenko wrote:
> > On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
> > > + ret = upboard_init_gpio(dev);
> > > + if (ret) {
> > > + if (ret != -EPROBE_DEFER)
> > > +
On Thu, Oct 25, 2018 at 12:05:05PM +0100, Lee Jones wrote:
> On Sat, 20 Oct 2018, Andy Shevchenko wrote:
> > On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
> > > + ret = upboard_init_gpio(dev);
> > > + if (ret) {
> > > + if (ret != -EPROBE_DEFER)
> > > +
On Sat, 20 Oct 2018, Andy Shevchenko wrote:
> On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
> >
> > From: Javier Arteaga
> >
> > UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
> > features a MAX 10 FPGA that routes lines from both SoC and on-board
> > devices to
On Sat, 20 Oct 2018, Andy Shevchenko wrote:
> On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
> >
> > From: Javier Arteaga
> >
> > UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
> > features a MAX 10 FPGA that routes lines from both SoC and on-board
> > devices to
On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
>
> From: Javier Arteaga
>
> UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
> features a MAX 10 FPGA that routes lines from both SoC and on-board
> devices to two I/O headers:
>
>
On Fri, Oct 19, 2018 at 8:26 PM Dan O'Donovan wrote:
>
> From: Javier Arteaga
>
> UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
> features a MAX 10 FPGA that routes lines from both SoC and on-board
> devices to two I/O headers:
>
>
From: Javier Arteaga
UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
features a MAX 10 FPGA that routes lines from both SoC and on-board
devices to two I/O headers:
++
| 40-pin
From: Javier Arteaga
UP Squared (UP2) is a x86 SBC from AAEON based on Intel Apollo Lake. It
features a MAX 10 FPGA that routes lines from both SoC and on-board
devices to two I/O headers:
++
| 40-pin
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