On Wed, 19 Dec 2018 at 16:30, Valentin Schneider
wrote:
>
> On 19/12/2018 15:20, Vincent Guittot wrote:
> [...]
> >> Oh yes, I never said it didn't work - I was doing some investigation on
> >> the reason as to why we'd need this fix, because it's wasn't explicit from
> >> the commit message.
>
On 19/12/2018 15:20, Vincent Guittot wrote:
[...]
>> Oh yes, I never said it didn't work - I was doing some investigation on
>> the reason as to why we'd need this fix, because it's wasn't explicit from
>> the commit message.
>>
>> The rounding errors are countered by the +1, yes, but I'd rather
On Wed, 19 Dec 2018 at 16:11, Valentin Schneider
wrote:
>
> On 19/12/2018 15:05, Vincent Guittot wrote:
> [...]
> >> True, I had a look at the trace and there doesn't seem to be any running
> >> task on that CPU. That's a separate matter however - the rounding issues
> >> can happen regardless of
On 19/12/2018 15:05, Vincent Guittot wrote:
[...]
>> True, I had a look at the trace and there doesn't seem to be any running
>> task on that CPU. That's a separate matter however - the rounding issues
>> can happen regardless of the wl values.
>
> But it means that the rounding fix +1 works and
On Wed, 19 Dec 2018 at 15:59, Valentin Schneider
wrote:
>
>
>
> On 19/12/2018 13:39, Vincent Guittot wrote:
> [...]
> >> I used that setup out of convenience for myself, but AFAICT that use-case
> >> just stresses that issue.
> >
> > After looking at you UC in details, your problem comes from the
On 19/12/2018 13:39, Vincent Guittot wrote:
[...]
>> I used that setup out of convenience for myself, but AFAICT that use-case
>> just stresses that issue.
>
> After looking at you UC in details, your problem comes from the wl=1
> for cpu0 whereas there is no running task.
> But wl!=0 without
On Wed, 19 Dec 2018 at 12:58, Valentin Schneider
wrote:
>
> On 19/12/2018 08:32, Vincent Guittot wrote:
> [...]
> > This is another UC, asym packing is used at SMT level for now and we
> > don't face this kind of problem, it has been also tested and DynamiQ
> > configuration which is similar to
On 19/12/2018 08:32, Vincent Guittot wrote:
[...]
> This is another UC, asym packing is used at SMT level for now and we
> don't face this kind of problem, it has been also tested and DynamiQ
> configuration which is similar to SMT : 1 CPU per sched_group
> The legacy b.L one was not the main
On Tue, 18 Dec 2018 at 18:32, Valentin Schneider
wrote:
>
> On 14/12/2018 16:01, Vincent Guittot wrote:
> > When check_asym_packing() is triggered, the imbalance is set to :
> > busiest_stat.avg_load * busiest_stat.group_capacity / SCHED_CAPACITY_SCALE
> > busiest_stat.avg_load also comes from a
On 14/12/2018 16:01, Vincent Guittot wrote:
> When check_asym_packing() is triggered, the imbalance is set to :
> busiest_stat.avg_load * busiest_stat.group_capacity / SCHED_CAPACITY_SCALE
> busiest_stat.avg_load also comes from a division and the final rounding
> can make imbalance slightly lower
When check_asym_packing() is triggered, the imbalance is set to :
busiest_stat.avg_load * busiest_stat.group_capacity / SCHED_CAPACITY_SCALE
busiest_stat.avg_load also comes from a division and the final rounding
can make imbalance slightly lower than the weighted load of the cfs_rq.
But this is
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