Re: [PATCH v2 1/4] mmc: sdhci-msm: fix issue with power irq

2017-10-03 Thread Adrian Hunter
On 27/09/17 08:34, Vijay Viswanath wrote: > From: Subhash Jadavani > > SDCC controller reset (SW_RST) during probe may trigger power irq if > previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we > enable the power irq interrupt in GIC (by registering

Re: [PATCH v2 1/4] mmc: sdhci-msm: fix issue with power irq

2017-10-03 Thread Adrian Hunter
On 27/09/17 08:34, Vijay Viswanath wrote: > From: Subhash Jadavani > > SDCC controller reset (SW_RST) during probe may trigger power irq if > previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we > enable the power irq interrupt in GIC (by registering the interrupt > handler),

[PATCH v2 1/4] mmc: sdhci-msm: fix issue with power irq

2017-09-26 Thread Vijay Viswanath
From: Subhash Jadavani SDCC controller reset (SW_RST) during probe may trigger power irq if previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we enable the power irq interrupt in GIC (by registering the interrupt handler), we need to ensure that any

[PATCH v2 1/4] mmc: sdhci-msm: fix issue with power irq

2017-09-26 Thread Vijay Viswanath
From: Subhash Jadavani SDCC controller reset (SW_RST) during probe may trigger power irq if previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we enable the power irq interrupt in GIC (by registering the interrupt handler), we need to ensure that any pending power irq interrupt