On Thu, Nov 05, 2015 at 05:59:36PM +0530, Vignesh R wrote:
> On 11/04/2015 08:09 PM, Mark Brown wrote:
> > It's a bit worrying that this doesn't sync with the message queue except
> > via the mutex: this means that we might be out of order with respect to
> > any asynchronous transfers that are
On 11/04/2015 08:09 PM, Mark Brown wrote:
> On Tue, Nov 03, 2015 at 03:36:10PM +0530, Vignesh R wrote:
>
>> +}
>> +mutex_lock(>mmap_lock_mutex);
>> +ret = master->spi_mtd_mmap_read(spi, from, len, retlen, buf,
>> +read_opcode, addr_width,
>> +
On 11/04/2015 08:09 PM, Mark Brown wrote:
> On Tue, Nov 03, 2015 at 03:36:10PM +0530, Vignesh R wrote:
>
>> +}
>> +mutex_lock(>mmap_lock_mutex);
>> +ret = master->spi_mtd_mmap_read(spi, from, len, retlen, buf,
>> +read_opcode, addr_width,
>> +
On Thu, Nov 05, 2015 at 05:59:36PM +0530, Vignesh R wrote:
> On 11/04/2015 08:09 PM, Mark Brown wrote:
> > It's a bit worrying that this doesn't sync with the message queue except
> > via the mutex: this means that we might be out of order with respect to
> > any asynchronous transfers that are
On Tue, Nov 03, 2015 at 03:36:10PM +0530, Vignesh R wrote:
> + }
> + mutex_lock(>mmap_lock_mutex);
> + ret = master->spi_mtd_mmap_read(spi, from, len, retlen, buf,
> + read_opcode, addr_width,
> + dummy_bytes);
>
On Tue, Nov 03, 2015 at 03:36:10PM +0530, Vignesh R wrote:
> + }
> + mutex_lock(>mmap_lock_mutex);
> + ret = master->spi_mtd_mmap_read(spi, from, len, retlen, buf,
> + read_opcode, addr_width,
> + dummy_bytes);
>
Hi,
On 11/03/2015 04:49 PM, Michal Suchanek wrote:
> On 3 November 2015 at 11:06, Vignesh R wrote:
>> In addition to providing direct access to SPI bus, some spi controller
>> hardwares (like ti-qspi) provide special memory mapped port
>> to accesses SPI flash devices in order to increase read
On 3 November 2015 at 11:06, Vignesh R wrote:
> In addition to providing direct access to SPI bus, some spi controller
> hardwares (like ti-qspi) provide special memory mapped port
> to accesses SPI flash devices in order to increase read performance.
> This means the controller can automatically
In addition to providing direct access to SPI bus, some spi controller
hardwares (like ti-qspi) provide special memory mapped port
to accesses SPI flash devices in order to increase read performance.
This means the controller can automatically send the SPI signals
required to read data from the
In addition to providing direct access to SPI bus, some spi controller
hardwares (like ti-qspi) provide special memory mapped port
to accesses SPI flash devices in order to increase read performance.
This means the controller can automatically send the SPI signals
required to read data from the
On 3 November 2015 at 11:06, Vignesh R wrote:
> In addition to providing direct access to SPI bus, some spi controller
> hardwares (like ti-qspi) provide special memory mapped port
> to accesses SPI flash devices in order to increase read performance.
> This means the controller
Hi,
On 11/03/2015 04:49 PM, Michal Suchanek wrote:
> On 3 November 2015 at 11:06, Vignesh R wrote:
>> In addition to providing direct access to SPI bus, some spi controller
>> hardwares (like ti-qspi) provide special memory mapped port
>> to accesses SPI flash devices in order
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