On Fri, May 08, 2020 at 11:22:36AM +0200, Thomas Bogendoerfer wrote:
> On Thu, May 07, 2020 at 10:13:37PM +0300, Serge Semin wrote:
> > On Thu, May 07, 2020 at 01:09:51PM +0200, Thomas Bogendoerfer wrote:
> > > On Wed, May 06, 2020 at 08:42:29PM +0300,
> > > sergey.se...@baikalelectronics.ru wrote
On Thu, May 07, 2020 at 10:13:37PM +0300, Serge Semin wrote:
> On Thu, May 07, 2020 at 01:09:51PM +0200, Thomas Bogendoerfer wrote:
> > On Wed, May 06, 2020 at 08:42:29PM +0300, sergey.se...@baikalelectronics.ru
> > wrote:
> > > From: Serge Semin
> > >
> > > Indeed according to the P5600/P6000 m
On Thu, May 07, 2020 at 01:09:51PM +0200, Thomas Bogendoerfer wrote:
> On Wed, May 06, 2020 at 08:42:29PM +0300, sergey.se...@baikalelectronics.ru
> wrote:
> > From: Serge Semin
> >
> > Indeed according to the P5600/P6000 manual the MAAR pair register
> > address field either takes [12:31] bits
On Wed, May 06, 2020 at 08:42:29PM +0300, sergey.se...@baikalelectronics.ru
wrote:
> From: Serge Semin
>
> Indeed according to the P5600/P6000 manual the MAAR pair register
> address field either takes [12:31] bits for 32-bits non-XPA systems
> and [12:35] otherwise. In any case the current addr
From: Serge Semin
Indeed according to the P5600/P6000 manual the MAAR pair register
address field either takes [12:31] bits for 32-bits non-XPA systems
and [12:35] otherwise. In any case the current address mask is just
wrong for 64-bit and 32-bits XPA chips. So lets extend it to 39-bits
value. T
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