Hi Rob, Marc,
On Fri, 8 Jun 2018 16:46:23 +0200, Miquel Raynal
wrote:
> Hi Rob, Marc,
>
> On Tue, 5 Jun 2018 14:51:21 -0600, Rob Herring wrote:
>
> > On Tue, May 22, 2018 at 11:40:39AM +0200, Miquel Raynal wrote:
> > > Describe the System Error Interrupt (SEI) controller. It aggregates two
Hi Rob, Marc,
On Tue, 5 Jun 2018 14:51:21 -0600, Rob Herring wrote:
> On Tue, May 22, 2018 at 11:40:39AM +0200, Miquel Raynal wrote:
> > Describe the System Error Interrupt (SEI) controller. It aggregates two
> > types of interrupts, wired and MSIs from respectively the AP and the
> > CPs, into
On Tue, May 22, 2018 at 11:40:39AM +0200, Miquel Raynal wrote:
> Describe the System Error Interrupt (SEI) controller. It aggregates two
> types of interrupts, wired and MSIs from respectively the AP and the
> CPs, into a single SPI interrupt.
>
> Suggested-by: Haim Boot
> Signed-off-by: Miquel R
Describe the System Error Interrupt (SEI) controller. It aggregates two
types of interrupts, wired and MSIs from respectively the AP and the
CPs, into a single SPI interrupt.
Suggested-by: Haim Boot
Signed-off-by: Miquel Raynal
---
.../bindings/interrupt-controller/marvell,sei.txt | 50 +++
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