While enabling undefined length INCR burst type and INCR16 burst type,
get better write performance on NXP Layerscape platform:
around 3% improvement (from 364MB/s to 375MB/s).
Signed-off-by: Changming Huang <jerry.hu...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
Changs in v2:
- split patch
- create one new function to handle soc bus configuration register
drivers/usb/dwc3/core.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 369bab1..699a409 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -991,6 +991,20 @@ static void dwc3_get_properties(struct dwc3 *dwc)
dwc->imod_interval = 0;
}
+/* set global soc bus configuration registers */
+static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
+{
+ u32 cfg;
+
+ cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+
+ /* Enable Undefined Length INCR Burst Type and Enable INCR16 Burst */
+ cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
+ cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA | DWC3_GSBUSCFG0_INCRBRSTENA;
+
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+}
+
/* check whether the core supports IMOD */
bool dwc3_has_imod(struct dwc3 *dwc)
{
@@ -1134,6 +1148,8 @@ static int dwc3_probe(struct platform_device *pdev)
goto err4;
}
+ dwc3_set_soc_bus_cfg(dwc);
+
dwc3_check_params(dwc);
ret = dwc3_core_init_mode(dwc);
--
1.7.9.5
