HI Jerome
On 07/16/18 17:54, Jerome Brunet wrote:
>
+/* uart_ao_a_ee */
+static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
+static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
>>>
>>> Same comment as Martin about naming consistency ... drop c2
HI Jerome
On 07/16/18 17:54, Jerome Brunet wrote:
>
+/* uart_ao_a_ee */
+static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
+static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
>>>
>>> Same comment as Martin about naming consistency ... drop c2
> > > +/* uart_ao_a_ee */
> > > +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
> > > +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
> >
> > Same comment as Martin about naming consistency ... drop c2 and c3 here.
> >
>
> there is already
> > > +/* uart_ao_a_ee */
> > > +static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
> > > +static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
> >
> > Same comment as Martin about naming consistency ... drop c2 and c3 here.
> >
>
> there is already
Hi Jerome
thanks for the review, see my comments below
On 07/16/18 00:16, Jerome Brunet wrote:
> On Sat, 2018-07-14 at 23:27 +, Yixun Lan wrote:
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
>>
>> Starting from Meson-AXG SoC, the
Hi Jerome
thanks for the review, see my comments below
On 07/16/18 00:16, Jerome Brunet wrote:
> On Sat, 2018-07-14 at 23:27 +, Yixun Lan wrote:
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
>>
>> Starting from Meson-AXG SoC, the
On Sat, 2018-07-14 at 23:27 +, Yixun Lan wrote:
> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
> the previous Meson-AXG SoC.
>
> Starting from Meson-AXG SoC, the pinctrl controller block use 4
> continues register bits to specific the pin mux function, while
On Sat, 2018-07-14 at 23:27 +, Yixun Lan wrote:
> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
> the previous Meson-AXG SoC.
>
> Starting from Meson-AXG SoC, the pinctrl controller block use 4
> continues register bits to specific the pin mux function, while
Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC.
Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register
Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC.
Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register
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