Re: [PATCH v2 2/3] clk: tegra: Add sdmmc mux divider clock

2018-07-09 Thread Peter De Schrijver
On Fri, Jul 06, 2018 at 11:18:30AM -0700, Stephen Boyd wrote: > Quoting Aapo Vienamo (2018-07-04 03:17:34) > > diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c > > b/drivers/clk/tegra/clk-sdmmc-mux.c > > new file mode 100644 > > index 000..8e19cb3 > > --- /dev/null > > +++ b/drivers/clk/tegra/cl

Re: [PATCH v2 2/3] clk: tegra: Add sdmmc mux divider clock

2018-07-06 Thread Stephen Boyd
Quoting Aapo Vienamo (2018-07-04 03:17:34) > diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c > b/drivers/clk/tegra/clk-sdmmc-mux.c > new file mode 100644 > index 000..8e19cb3 > --- /dev/null > +++ b/drivers/clk/tegra/clk-sdmmc-mux.c > @@ -0,0 +1,254 @@ > +/* > + * Copyright (c) 2018 NVIDIA CORP

[PATCH v2 2/3] clk: tegra: Add sdmmc mux divider clock

2018-07-04 Thread Aapo Vienamo
From: Peter De-Schrijver Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider