Re: [PATCH v2 2/4] mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset

2017-10-03 Thread Adrian Hunter
On 27/09/17 08:34, Vijay Viswanath wrote: > From: Sahitya Tummala > > There is a rare scenario in HW, where the first clear pulse could > be lost when the actual reset and clear/read of status register > are happening at the same time. Fix this by retrying upto 10 times

Re: [PATCH v2 2/4] mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset

2017-10-03 Thread Adrian Hunter
On 27/09/17 08:34, Vijay Viswanath wrote: > From: Sahitya Tummala > > There is a rare scenario in HW, where the first clear pulse could > be lost when the actual reset and clear/read of status register > are happening at the same time. Fix this by retrying upto 10 times > to ensure the status

[PATCH v2 2/4] mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset

2017-09-26 Thread Vijay Viswanath
From: Sahitya Tummala There is a rare scenario in HW, where the first clear pulse could be lost when the actual reset and clear/read of status register are happening at the same time. Fix this by retrying upto 10 times to ensure the status register gets cleared.

[PATCH v2 2/4] mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset

2017-09-26 Thread Vijay Viswanath
From: Sahitya Tummala There is a rare scenario in HW, where the first clear pulse could be lost when the actual reset and clear/read of status register are happening at the same time. Fix this by retrying upto 10 times to ensure the status register gets cleared. Otherwise, this will lead to a