ead.org; John Linn; a...@kernel.org
> Subject: Re: [PATCH v2 2/5] clk: Add support for fundamental zynq clks
>
> On Thu, Nov 08, 2012 at 03:28:07PM -0800, Soren Brinkmann wrote:
> > One note below:
> >
> > On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
> [..]
> &
Subject: Re: [PATCH v2 2/5] clk: Add support for fundamental zynq clks
On Thu, Nov 08, 2012 at 03:28:07PM -0800, Soren Brinkmann wrote:
One note below:
On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
[..]
--- /dev/null
+++ b/drivers/clk/clk-zynq.c
[..]
+struct
On Thu, Nov 08, 2012 at 03:28:07PM -0800, Soren Brinkmann wrote:
> One note below:
>
> On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
[..]
> > --- /dev/null
> > +++ b/drivers/clk/clk-zynq.c
[..]
> > +struct zynq_periph_clk {
> > + struct clk_hw hw;
> > + struct
On Thu, Nov 08, 2012 at 03:28:07PM -0800, Soren Brinkmann wrote:
One note below:
On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
[..]
--- /dev/null
+++ b/drivers/clk/clk-zynq.c
[..]
+struct zynq_periph_clk {
+ struct clk_hw hw;
+ struct clk_onecell_data
l Simek; John Linn; a...@kernel.org
> Subject: Re: [PATCH v2 2/5] clk: Add support for fundamental zynq clks
>
> One note below:
>
> On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
> > Provide simplified models for the necessary clocks on the zynq-7000
> > platform
Subject: Re: [PATCH v2 2/5] clk: Add support for fundamental zynq clks
One note below:
On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
One note below:
On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
> Provide simplified models for the necessary clocks on the zynq-7000
> platform. Currently, the PLLs, the CPU clock network, and the basic
> peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
OF bindings are also provided and documented.
Signed-off-by: Josh Cartwright
---
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
OF bindings are also provided and documented.
Signed-off-by: Josh Cartwright
One note below:
On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
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