From: Biwen Li <biwen...@nxp.com> Hardware issue: - Reading register RCPM_IPPDEXPCR1 always return zero, this causes system firmware could not get correct information and wrongly do clock gating for all wakeup source IP during system suspend. Then those IPs will never get chance to wake system.
Workaround: - Duplicate register RCPM_IPPDEXPCR1's setting to register SCFG_SPARECR8 to allow system firmware's psci method read it and do things accordingly. Signed-off-by: Biwen Li <biwen...@nxp.com> Signed-off-by: Ran Wang <ran.wan...@nxp.com> --- Change in v2: - Update commit message to be more clear. - Replace device_property_read_u32_array() with syscon_regmap_lookup_by_phandle_args() to make code simpler. drivers/soc/fsl/rcpm.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c index a093dbe..6e37777 100644 --- a/drivers/soc/fsl/rcpm.c +++ b/drivers/soc/fsl/rcpm.c @@ -2,7 +2,7 @@ // // rcpm.c - Freescale QorIQ RCPM driver // -// Copyright 2019 NXP +// Copyright 2019-2020 NXP // // Author: Ran Wang <ran.wan...@nxp.com> @@ -13,6 +13,9 @@ #include <linux/slab.h> #include <linux/suspend.h> #include <linux/kernel.h> +#include <linux/acpi.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> #define RCPM_WAKEUP_CELL_MAX_SIZE 7 @@ -37,6 +40,9 @@ static int rcpm_pm_prepare(struct device *dev) struct device_node *np = dev->of_node; u32 value[RCPM_WAKEUP_CELL_MAX_SIZE + 1]; u32 setting[RCPM_WAKEUP_CELL_MAX_SIZE] = {0}; + struct regmap *scfg_addr_regmap = NULL; + u32 reg_offset = 0; + u32 reg_value = 0; rcpm = dev_get_drvdata(dev); if (!rcpm) @@ -90,6 +96,29 @@ static int rcpm_pm_prepare(struct device *dev) tmp |= ioread32be(address); iowrite32be(tmp, address); } + /* + * Workaround of errata A-008646 on SoC LS1021A: + * There is a bug of register ippdexpcr1. + * Reading configuration register RCPM_IPPDEXPCR1 + * always return zero. So save ippdexpcr1's value + * to register SCFG_SPARECR8.And the value of + * ippdexpcr1 will be read from SCFG_SPARECR8. + */ + if (dev_of_node(dev) && (i == 1)) { + scfg_addr_regmap = syscon_regmap_lookup_by_phandle_args(np, + "fsl,ippdexpcr1-alt-addr", + 1, + ®_offset); + if (!IS_ERR_OR_NULL(scfg_addr_regmap)) { + /* Update value on register SCFG_SPARECR8 */ + regmap_read(scfg_addr_regmap, + reg_offset, + ®_value); + regmap_write(scfg_addr_regmap, + reg_offset, + tmp | reg_value); + } + } } return 0; -- 2.7.4