On Tue, Apr 19, 2016 at 10:00 AM, Maxime Coquelin
wrote:
> 2016-04-08 11:38 GMT+02:00 Linus Walleij :
>> while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
>> irq = ffs(stat) - 1;
>>
On Tue, Apr 19, 2016 at 10:00 AM, Maxime Coquelin
wrote:
> 2016-04-08 11:38 GMT+02:00 Linus Walleij :
>> while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
>> irq = ffs(stat) - 1;
>> handle_domain_irq(vic->domain, irq, regs);
>>
Hi Linus,
Sorry for the late reply, I was off last week.
2016-04-08 11:38 GMT+02:00 Linus Walleij :
> On Thu, Mar 31, 2016 at 5:09 PM, Maxime Coquelin
> wrote:
>
>> +static void stm32_irq_handler(struct irq_desc *desc)
>> +{
>> + struct
Hi Linus,
Sorry for the late reply, I was off last week.
2016-04-08 11:38 GMT+02:00 Linus Walleij :
> On Thu, Mar 31, 2016 at 5:09 PM, Maxime Coquelin
> wrote:
>
>> +static void stm32_irq_handler(struct irq_desc *desc)
>> +{
>> + struct irq_domain *domain =
On Thu, Mar 31, 2016 at 5:09 PM, Maxime Coquelin
wrote:
> + gc = domain->gc->gc[0];
> + gc->reg_base = base;
> + gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
> + gc->chip_types->chip.name =
On Thu, Mar 31, 2016 at 5:09 PM, Maxime Coquelin
wrote:
> + gc = domain->gc->gc[0];
> + gc->reg_base = base;
> + gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
> + gc->chip_types->chip.name = gc->chip_types[0].chip.name;
> +
On Thu, Mar 31, 2016 at 5:09 PM, Maxime Coquelin
wrote:
> +static void stm32_irq_handler(struct irq_desc *desc)
> +{
> + struct irq_domain *domain = irq_desc_get_handler_data(desc);
> + struct irq_chip_generic *gc = domain->gc->gc[0];
> + struct
On Thu, Mar 31, 2016 at 5:09 PM, Maxime Coquelin
wrote:
> +static void stm32_irq_handler(struct irq_desc *desc)
> +{
> + struct irq_domain *domain = irq_desc_get_handler_data(desc);
> + struct irq_chip_generic *gc = domain->gc->gc[0];
> + struct irq_chip *chip =
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, fallin or both edges. Each line can also
be masked independently.
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, fallin or both edges. Each line can also
be masked independently.
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