Re: [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles from nv cfg reg

2017-10-16 Thread matthew . gerlach
Hi Cyrille, Thanks for the feedback. See my comments in line below. Matthew Gerlach On Tue, 10 Oct 2017, Cyrille Pitchen wrote: Hi Matthew NAK for this patch Le 20/09/2017 à 20:28, matthew.gerl...@linux.intel.com a écrit : From: Matthew Gerlach This patch is a work around for some non

Re: [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles from nv cfg reg

2017-10-10 Thread Cyrille Pitchen
Hi Matthew NAK for this patch Le 20/09/2017 à 20:28, matthew.gerl...@linux.intel.com a écrit : > From: Matthew Gerlach > > This patch is a work around for some non-standard behavior > of EPCQ flash parts: > > https://www.altera.com/documentation/wtw1396921531042.html#wtw1396921651224 > >From

[PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles from nv cfg reg

2017-09-20 Thread matthew . gerlach
From: Matthew Gerlach This patch is a work around for some non-standard behavior of EPCQ flash parts: https://www.altera.com/documentation/wtw1396921531042.html#wtw1396921651224 These flash parts are generally used to configure Intel/Altera FPGAs on power up. These parts report a JEDEC id of t