Hi Sunny,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on spi/for-next]
[also build test WARNING on v4.20-rc6 next-20181214]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
On Thu, 2018-12-13 at 22:37 +0800, Sunny Luo wrote:
> Hi Jerome,
>
> On 2018/12/13 17:28, Jerome Brunet wrote:
> > On Thu, 2018-12-13 at 09:55 +0100, Neil Armstrong wrote:
> > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > > > config SPI_MESON_SPICC
> > > > tristate
Hi Jerome,
On 2018/12/13 17:28, Jerome Brunet wrote:
On Thu, 2018-12-13 at 09:55 +0100, Neil Armstrong wrote:
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
config SPI_MESON_SPICC
tristate "Amlogic Meson SPICC controller"
- depends on ARCH_MESON || COMPILE_TEST
+
Hi Neil,
On 2018/12/13 16:55, Neil Armstrong wrote:
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider,
On Thu, 2018-12-13 at 09:55 +0100, Neil Armstrong wrote:
> Hi Sunny,
>
> On 13/12/2018 09:39, Sunny Luo wrote:
> > The SPICC controller in Meson-AXG SoC is capable of using
> > a linear clock divider to reach a much fine tuned range of clocks,
> > while the old controller only use a power of two
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
> The SPICC controller in Meson-AXG SoC is capable of using
> a linear clock divider to reach a much fine tuned range of clocks,
> while the old controller only use a power of two clock divider,
> result at a more coarse clock range.
This patch
The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider,
result at a more coarse clock range.
Also convert the clock registration into Common Clock Framework.
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