Re: [PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-30 Thread Andy Shevchenko
On Tue, Oct 30, 2018 at 9:40 AM Bhardwaj, Rajneesh wrote: > Thanks for your review. My comments below. > > If you agree then i can quickly send v3 addressing all suggestions so we > can make it in time for 4.20 merge window. I don't like `quickly` part — usual way to make the last minute

Re: [PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-30 Thread Andy Shevchenko
On Tue, Oct 30, 2018 at 9:40 AM Bhardwaj, Rajneesh wrote: > Thanks for your review. My comments below. > > If you agree then i can quickly send v3 addressing all suggestions so we > can make it in time for 4.20 merge window. I don't like `quickly` part — usual way to make the last minute

Re: [PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-30 Thread Bhardwaj, Rajneesh
Hi Andy, Thanks for your review. My comments below. If you agree then i can quickly send v3 addressing all suggestions so we can make it in time for 4.20 merge window. On 19-Oct-18 6:04 PM, Andy Shevchenko wrote: On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj wrote: The LTR values

Re: [PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-30 Thread Bhardwaj, Rajneesh
Hi Andy, Thanks for your review. My comments below. If you agree then i can quickly send v3 addressing all suggestions so we can make it in time for 4.20 merge window. On 19-Oct-18 6:04 PM, Andy Shevchenko wrote: On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj wrote: The LTR values

Re: [PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-19 Thread Andy Shevchenko
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj wrote: > > The LTR values follow PCIE LTR encoding format and can be decoded as per > https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf > > This adds support to translate the raw LTR values as read

Re: [PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-19 Thread Andy Shevchenko
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj wrote: > > The LTR values follow PCIE LTR encoding format and can be decoded as per > https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf > > This adds support to translate the raw LTR values as read

[PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-06 Thread Rajneesh Bhardwaj
The LTR values follow PCIE LTR encoding format and can be decoded as per https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf This adds support to translate the raw LTR values as read from the PMC to meaningful values in nanosecond units of time.

[PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-10-06 Thread Rajneesh Bhardwaj
The LTR values follow PCIE LTR encoding format and can be decoded as per https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf This adds support to translate the raw LTR values as read from the PMC to meaningful values in nanosecond units of time.