Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Thu, Oct 5, 2017 at 6:48 AM, Stephen Boyd wrote: > On 10/03, Joel Stanley wrote: >> On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote: >> > On 09/21, Joel Stanley wrote: >> >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Thu, Oct 5, 2017 at 6:48 AM, Stephen Boyd wrote: > On 10/03, Joel Stanley wrote: >> On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote: >> > On 09/21, Joel Stanley wrote: >> >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char >> >> *name, u32 val) >> >> + /* >> >> +

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On 10/03, Joel Stanley wrote: > On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote: > > On 09/21, Joel Stanley wrote: > >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char > >> *name, u32 val) > >> + /* > >> + * Memory controller (M-PLL) PLL.

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On 10/03, Joel Stanley wrote: > On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote: > > On 09/21, Joel Stanley wrote: > >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char > >> *name, u32 val) > >> + /* > >> + * Memory controller (M-PLL) PLL. This clock is

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote: > On 09/21, Joel Stanley wrote: >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char >> *name, u32 val) >> + /* >> + * Memory controller (M-PLL) PLL. This clock is configured by the >> +

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote: > On 09/21, Joel Stanley wrote: >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char >> *name, u32 val) >> + /* >> + * Memory controller (M-PLL) PLL. This clock is configured by the >> + * bootloader, and is

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On 09/21, Joel Stanley wrote: > @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, > u32 val) > mult, div); > } > > +static int __init aspeed_clk_probe(struct platform_device *pdev) Drop __init? Should be a section mismatch with __init here. >

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On 09/21, Joel Stanley wrote: > @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, > u32 val) > mult, div); > } > > +static int __init aspeed_clk_probe(struct platform_device *pdev) Drop __init? Should be a section mismatch with __init here. >

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Wed, Sep 27, 2017 at 5:34 PM, Andrew Jeffery wrote: > On Wed, 2017-09-27 at 16:13 +1000, Joel Stanley wrote: >> > > + div_table, >> > >> > This doesn't seem to be correct. There's the problem of 0b000 and 0b001 >> > mapping >> > the same value of 2 for the

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Wed, Sep 27, 2017 at 5:34 PM, Andrew Jeffery wrote: > On Wed, 2017-09-27 at 16:13 +1000, Joel Stanley wrote: >> > > + div_table, >> > >> > This doesn't seem to be correct. There's the problem of 0b000 and 0b001 >> > mapping >> > the same value of 2 for the AST2500, whose

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Wed, 2017-09-27 at 16:13 +1000, Joel Stanley wrote: > > > + div_table, > > > > This doesn't seem to be correct. There's the problem of 0b000 and 0b001 > > mapping > > the same value of 2 for the AST2500, whose table then increments in steps > > of 1. > > The AST2400

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Wed, 2017-09-27 at 16:13 +1000, Joel Stanley wrote: > > > + div_table, > > > > This doesn't seem to be correct. There's the problem of 0b000 and 0b001 > > mapping > > the same value of 2 for the AST2500, whose table then increments in steps > > of 1. > > The AST2400

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Mon, Sep 25, 2017 at 10:40 PM, Andrew Jeffery wrote: > On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote: >> + /* >> + * Memory controller (M-PLL) PLL. This clock is configured by the >> + * bootloader, and is exposed to Linux as a read-only clock rate. >> +

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Mon, Sep 25, 2017 at 10:40 PM, Andrew Jeffery wrote: > On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote: >> + /* >> + * Memory controller (M-PLL) PLL. This clock is configured by the >> + * bootloader, and is exposed to Linux as a read-only clock rate. >> + */ >> +

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote: > This registers a platform driver to set up all of the non-core clocks. >  > The clocks that have configurable rates are now registered. >  > Signed-off-by: Joel Stanley > --- >  drivers/clk/clk-aspeed.c | 129 >

Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote: > This registers a platform driver to set up all of the non-core clocks. >  > The clocks that have configurable rates are now registered. >  > Signed-off-by: Joel Stanley > --- >  drivers/clk/clk-aspeed.c | 129 >

[PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 129 +++ 1 file changed, 129 insertions(+)

[PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs

This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 129 +++ 1 file changed, 129 insertions(+) diff --git