[PATCH v2 4/4] clk: tegra20: Bump SCLK clock rate to 216MHz

AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 file changed, 1

[PATCH v2 4/4] clk: tegra20: Bump SCLK clock rate to 216MHz

AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git