Re: [PATCH v2 4/5] clk: aspeed: Register gated clocks

2017-10-02 Thread Joel Stanley
On Tue, Oct 3, 2017 at 7:07 AM, Stephen Boyd wrote: > On 09/21, Joel Stanley wrote: >> The majority of the clocks in the system are gates paired with a reset >> controller that holds the IP in reset. >> >> This borrows from clk_hw_register_gate, but registers two 'gates', one >> to control the clo

Re: [PATCH v2 4/5] clk: aspeed: Register gated clocks

2017-10-02 Thread Stephen Boyd
On 09/21, Joel Stanley wrote: > The majority of the clocks in the system are gates paired with a reset > controller that holds the IP in reset. > > This borrows from clk_hw_register_gate, but registers two 'gates', one > to control the clock enable register and the other to control the reset > IP.

[PATCH v2 4/5] clk: aspeed: Register gated clocks

2017-09-20 Thread Joel Stanley
The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: