On Tue, 2020-08-11 at 15:28 +0800, Nicolas Boichat wrote:
> On Tue, Aug 11, 2020 at 2:43 PM Weiyi Lu wrote:
> > [...]
> > > > + writel(r, pll->en_addr);
> > > >
> > > > r = readl(pll->pwr_addr) | CON0_ISO_EN;
> > > > writel(r, pll->pwr_addr);
> > > > @@ -327,6 +327,10 @@ stat
On Tue, Aug 11, 2020 at 2:43 PM Weiyi Lu wrote:
> [...]
> > > + writel(r, pll->en_addr);
> > >
> > > r = readl(pll->pwr_addr) | CON0_ISO_EN;
> > > writel(r, pll->pwr_addr);
> > > @@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct
> > > mtk_pll_data *da
On Wed, 2020-07-29 at 18:58 +0800, Nicolas Boichat wrote:
> On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu wrote:
> >
> > In all MediaTek PLL design, bit0 of CON0 register is always
> > the enable bit.
> > However, there's a special case of usbpll on MT8192.
> > The enable bit of usbpll is moved to bit2
On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu wrote:
>
> In all MediaTek PLL design, bit0 of CON0 register is always
> the enable bit.
> However, there's a special case of usbpll on MT8192.
> The enable bit of usbpll is moved to bit2 of other register.
> Add configurable en_reg and pll_en_bit for enabl
In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
H
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