Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On Tue, May 29, 2018 at 03:19:47PM +0300, Dmitry Osipenko wrote: > On 29.05.2018 15:12, Stefan Agner wrote: > > On 29.05.2018 09:48, Peter De Schrijver wrote: > >> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: > >>> On 28.05.2018 09:55, Peter De Schrijver wrote: > On Sun, May

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On Tue, May 29, 2018 at 03:19:47PM +0300, Dmitry Osipenko wrote: > On 29.05.2018 15:12, Stefan Agner wrote: > > On 29.05.2018 09:48, Peter De Schrijver wrote: > >> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: > >>> On 28.05.2018 09:55, Peter De Schrijver wrote: > On Sun, May

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 29.05.2018 15:12, Stefan Agner wrote: > On 29.05.2018 09:48, Peter De Schrijver wrote: >> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: >>> On 28.05.2018 09:55, Peter De Schrijver wrote: On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > From: Lucas Stach

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 29.05.2018 15:12, Stefan Agner wrote: > On 29.05.2018 09:48, Peter De Schrijver wrote: >> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: >>> On 28.05.2018 09:55, Peter De Schrijver wrote: On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > From: Lucas Stach

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 29.05.2018 09:48, Peter De Schrijver wrote: > On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: >> On 28.05.2018 09:55, Peter De Schrijver wrote: >> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: >> >> From: Lucas Stach >> >> >> >> Set up the NAND Flash controller

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 29.05.2018 09:48, Peter De Schrijver wrote: > On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: >> On 28.05.2018 09:55, Peter De Schrijver wrote: >> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: >> >> From: Lucas Stach >> >> >> >> Set up the NAND Flash controller

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: > On 28.05.2018 09:55, Peter De Schrijver wrote: > > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > >> From: Lucas Stach > >> > >> Set up the NAND Flash controller clock to run at 150MHz > >> instead of the rate set by

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: > On 28.05.2018 09:55, Peter De Schrijver wrote: > > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > >> From: Lucas Stach > >> > >> Set up the NAND Flash controller clock to run at 150MHz > >> instead of the rate set by

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

Am Montag, den 28.05.2018, 17:53 +0200 schrieb Stefan Agner: > On 28.05.2018 09:55, Peter De Schrijver wrote: > > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > > > From: Lucas Stach > > > > > > Set up the NAND Flash controller clock to run at 150MHz > > >

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

Am Montag, den 28.05.2018, 17:53 +0200 schrieb Stefan Agner: > On 28.05.2018 09:55, Peter De Schrijver wrote: > > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > > > From: Lucas Stach > > > > > > Set up the NAND Flash controller clock to run at 150MHz > > > instead of the rate

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 28.05.2018 09:55, Peter De Schrijver wrote: > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: >> From: Lucas Stach >> >> Set up the NAND Flash controller clock to run at 150MHz >> instead of the rate set by the bootloader. This is a >> conservative rate which

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 28.05.2018 09:55, Peter De Schrijver wrote: > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: >> From: Lucas Stach >> >> Set up the NAND Flash controller clock to run at 150MHz >> instead of the rate set by the bootloader. This is a >> conservative rate which also yields good

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > From: Lucas Stach > > Set up the NAND Flash controller clock to run at 150MHz > instead of the rate set by the bootloader. This is a > conservative rate which also yields good performance. > > Signed-off-by: Lucas

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > From: Lucas Stach > > Set up the NAND Flash controller clock to run at 150MHz > instead of the rate set by the bootloader. This is a > conservative rate which also yields good performance. > > Signed-off-by: Lucas Stach >

[PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

From: Lucas Stach Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner ---

[PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

From: Lucas Stach Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner --- drivers/clk/tegra/clk-tegra20.c | 1 + 1 file