On Sun, 17 Jan 2021, Jeff LaBundy wrote:
> The time the device takes to deassert its RDY output following an
> I2C stop condition scales with the core clock frequency.
>
> To prevent level-triggered interrupts from being reasserted after
> the interrupt handler returns, increase the time before r
The time the device takes to deassert its RDY output following an
I2C stop condition scales with the core clock frequency.
To prevent level-triggered interrupts from being reasserted after
the interrupt handler returns, increase the time before returning
to account for the worst-case delay (~90 us
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