On Tue, Feb 11, 2014 at 07:31:59PM +0100, Stephane Eranian wrote:
> > Anyway, perf_event_intel.c lists: 60,63,69,70,71 as being haswell
> > clients. Andi did all that, so if its wrong its on Intel anyway.
> >
> What he has is okay for core. They all have the same core PMU at 99%.
> But the uncore
On Tue, Feb 11, 2014 at 5:50 PM, Peter Zijlstra wrote:
> On Tue, Feb 11, 2014 at 05:25:39PM +0100, Stephane Eranian wrote:
>> On Tue, Feb 11, 2014 at 5:19 PM, Peter Zijlstra wrote:
>> > On Tue, Feb 11, 2014 at 04:20:12PM +0100, Stephane Eranian wrote:
>> >> This patch adds a new uncore PMU for In
On Tue, Feb 11, 2014 at 05:25:39PM +0100, Stephane Eranian wrote:
> On Tue, Feb 11, 2014 at 5:19 PM, Peter Zijlstra wrote:
> > On Tue, Feb 11, 2014 at 04:20:12PM +0100, Stephane Eranian wrote:
> >> This patch adds a new uncore PMU for Intel SNB/IVB/HSW client
> >
> >
> >> @@ -3501,6 +3844,28 @@ st
On Tue, Feb 11, 2014 at 5:19 PM, Peter Zijlstra wrote:
> On Tue, Feb 11, 2014 at 04:20:12PM +0100, Stephane Eranian wrote:
>> This patch adds a new uncore PMU for Intel SNB/IVB/HSW client
>
>
>> @@ -3501,6 +3844,28 @@ static int __init uncore_pci_init(void)
>> pci_uncores = ivt_pci_u
On Tue, Feb 11, 2014 at 04:20:12PM +0100, Stephane Eranian wrote:
> This patch adds a new uncore PMU for Intel SNB/IVB/HSW client
> @@ -3501,6 +3844,28 @@ static int __init uncore_pci_init(void)
> pci_uncores = ivt_pci_uncores;
> uncore_pci_driver = &ivt_uncore_pci_dri
This patch adds a new uncore PMU for Intel SNB/IVB/HSW client
CPUs. It adds the Integrated Memory Controller (IMC) PMU. This
new PMU provides a set of events to measure memory bandwidth utilization.
The IMC on those processor is PCI-space based. This patch
exposes a new uncore PMU on those process
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