quot;
> + : "=&r" (ret), "=&r" (tmp)
> + : "r" (x), "r" (ptr)
> + : "memory", "cc");
> + break;
> +#endif
> case 4:
> asm vol
: "=&r" (ret), "=&r" (tmp)
+ : "r" (x), "r" (ptr)
+ : "memory", "cc");
+ break;
+#endif
case 4:
asm volatile("@ __xchg4\n"
On Fri, Oct 09, 2015 at 02:41:54AM +, Sarbojit Ganguly wrote:
> Thank you Will, I will make the required corrections and mail it to
> patchesAtarm.linux.co.uk and mark [1] as "superseded".
Thanks. Also, you don't need to continually prepend "Re: " to your mail
subject every time you reply and/
(GMT+05:30)
Title : Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word
exchange
On Wed, Oct 07, 2015 at 02:36:41PM +, Sarbojit Ganguly wrote:
> Please have a look at this patch, please let me know if any modification
> is required.
> I have also submitted the
On Wed, Oct 07, 2015 at 02:36:41PM +, Sarbojit Ganguly wrote:
> Please have a look at this patch, please let me know if any modification
> is required.
> I have also submitted the same in your patch system.
There are some problems with the version in the patch system[1]:
(1) You still have
;@ __xchg4\n"
"1: ldrex %0, [%3]\n"
--
1.9.1
Regards,
Sarbojit
--- Original Message ---
Sender : Will Deacon
Date : Oct 06, 2015 20:24 (GMT+05:30)
Title : Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word
exchange
On Tue, Oct 06, 20
On Tue, Oct 06, 2015 at 08:03:02AM +, Sarbojit Ganguly wrote:
> Here is the version 3 of the patch correcting earlier issues.
This looks good to me now:
Acked-by: Will Deacon
> v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to
> #ifndef.
> v1 -> v2 : Extended the gu
Hello Will
Here is the version 3 of the patch correcting earlier issues.
v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to
#ifndef.
v1 -> v2 : Extended the guard code to cover the byte exchange case as
well following opinion of Will Deacon.
Checkpatch has been run and issu
8 matches
Mail list logo
