On 08/01/15 17:30, Will Deacon wrote:
> Hi Daniel,
>
> Some minor comments below...
>
> On Wed, Jan 07, 2015 at 12:28:18PM +, Daniel Thompson wrote:
>> Some ARM platforms mux the PMU interrupt of every core into a single
>> SPI. On such platforms if the PMU of any core except 0 raises an inte
Hi Daniel,
Some minor comments below...
On Wed, Jan 07, 2015 at 12:28:18PM +, Daniel Thompson wrote:
> Some ARM platforms mux the PMU interrupt of every core into a single
> SPI. On such platforms if the PMU of any core except 0 raises an interrupt
> then it cannot be serviced and eventually,
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and eventually, if you are lucky, the spurious
irq detection might forcefully disable the interrupt.
On these SoCs it is not po
3 matches
Mail list logo