Re: [PATCH v3] clk: rockchip: switch PLLs to slow mode before reboot for rk3288

Hi Chris, Am Mittwoch, 11. November 2015, 15:09:59 schrieb Chris Zhong: > We've been seeing some crashes at reboot test on rk3288-based systems, > which boards have not reset pin connected to NPOR, they reboot by > setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in > a high

Re: [PATCH v3] clk: rockchip: switch PLLs to slow mode before reboot for rk3288

Hi Chris, Am Mittwoch, 11. November 2015, 15:09:59 schrieb Chris Zhong: > We've been seeing some crashes at reboot test on rk3288-based systems, > which boards have not reset pin connected to NPOR, they reboot by > setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in > a high

[PATCH v3] clk: rockchip: switch PLLs to slow mode before reboot for rk3288

We've been seeing some crashes at reboot test on rk3288-based systems, which boards have not reset pin connected to NPOR, they reboot by setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in a high frequency mode, some IPs might hang during soft reset. It appears that we can fix the

[PATCH v3] clk: rockchip: switch PLLs to slow mode before reboot for rk3288

We've been seeing some crashes at reboot test on rk3288-based systems, which boards have not reset pin connected to NPOR, they reboot by setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in a high frequency mode, some IPs might hang during soft reset. It appears that we can fix the