On 05/28/2014 11:01 AM, Linus Walleij wrote:
> On Tue, May 27, 2014 at 6:30 PM, Sebastian Andrzej Siewior
> wrote:
>
>> What remains in my queue is:
>>
>> * gpio: dwapb: use irq_linear_revmap() for the faster lookup
>> * gpio: dwapb: use irq_gc_lock() for locking instead bc's lock
>> * gpio:
On Tue, May 27, 2014 at 6:30 PM, Sebastian Andrzej Siewior
wrote:
> What remains in my queue is:
>
> * gpio: dwapb: use irq_linear_revmap() for the faster lookup
> * gpio: dwapb: use irq_gc_lock() for locking instead bc's lock
> * gpio: dwapb: use d->mask instead of BIT(bit)
>
> what do we do
On Tue, May 27, 2014 at 6:30 PM, Sebastian Andrzej Siewior
bige...@linutronix.de wrote:
What remains in my queue is:
* gpio: dwapb: use irq_linear_revmap() for the faster lookup
* gpio: dwapb: use irq_gc_lock() for locking instead bc's lock
* gpio: dwapb: use d-mask instead of BIT(bit)
On 05/28/2014 11:01 AM, Linus Walleij wrote:
On Tue, May 27, 2014 at 6:30 PM, Sebastian Andrzej Siewior
bige...@linutronix.de wrote:
What remains in my queue is:
* gpio: dwapb: use irq_linear_revmap() for the faster lookup
* gpio: dwapb: use irq_gc_lock() for locking instead bc's lock
*
On 05/27/2014 04:21 PM, Linus Walleij wrote:
> OK this version applied worked fine.
Thank you.
> Please check the result because I had to rebase it a little.
Looks good. What remains in my queue is:
* gpio: dwapb: use irq_linear_revmap() for the faster lookup
* gpio: dwapb: use irq_gc_lock()
On Mon, May 26, 2014 at 10:58 PM, Sebastian Andrzej Siewior
wrote:
> Right new have one irq chip running always in level mode. It would nicer
> to have two irq chips where one is handling level type interrupts and
> the other one is doing edge interrupts. So we can have at runtime two users
>
On Mon, May 26, 2014 at 10:58:14PM +0200, Sebastian Andrzej Siewior wrote:
> Right new have one irq chip running always in level mode. It would nicer
> to have two irq chips where one is handling level type interrupts and
> the other one is doing edge interrupts. So we can have at runtime two
On Mon, May 26, 2014 at 10:58:14PM +0200, Sebastian Andrzej Siewior wrote:
Right new have one irq chip running always in level mode. It would nicer
to have two irq chips where one is handling level type interrupts and
the other one is doing edge interrupts. So we can have at runtime two users
On Mon, May 26, 2014 at 10:58 PM, Sebastian Andrzej Siewior
bige...@linutronix.de wrote:
Right new have one irq chip running always in level mode. It would nicer
to have two irq chips where one is handling level type interrupts and
the other one is doing edge interrupts. So we can have at
On 05/27/2014 04:21 PM, Linus Walleij wrote:
OK this version applied worked fine.
Thank you.
Please check the result because I had to rebase it a little.
Looks good. What remains in my queue is:
* gpio: dwapb: use irq_linear_revmap() for the faster lookup
* gpio: dwapb: use irq_gc_lock() for
Right new have one irq chip running always in level mode. It would nicer
to have two irq chips where one is handling level type interrupts and
the other one is doing edge interrupts. So we can have at runtime two users
where one is using edge and the other level.
Acked-by: Alan Tull
Right new have one irq chip running always in level mode. It would nicer
to have two irq chips where one is handling level type interrupts and
the other one is doing edge interrupts. So we can have at runtime two users
where one is using edge and the other level.
Acked-by: Alan Tull
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