Marc Zyngier wrote:
> On 19/12/2018 18:37, Lubomir Rintel wrote:
>> On Wed, 2018-12-19 at 18:29 +, Marc Zyngier wrote:
>>> On 19/12/2018 17:28, Lubomir Rintel wrote:
On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
and 72 interrupts. Don't reset the "route to
On 19/12/2018 18:37, Lubomir Rintel wrote:
> On Wed, 2018-12-19 at 18:29 +, Marc Zyngier wrote:
>> On 19/12/2018 17:28, Lubomir Rintel wrote:
>>> On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
>>> and 72 interrupts. Don't reset the "route to SP" bit (4).
>>>
>>> I'm
On Wed, 2018-12-19 at 18:29 +, Marc Zyngier wrote:
> On 19/12/2018 17:28, Lubomir Rintel wrote:
> > On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
> > and 72 interrupts. Don't reset the "route to SP" bit (4).
> >
> > I'm just assuming the bit 4 is the "route to SP"
On 19/12/2018 17:28, Lubomir Rintel wrote:
> On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
> and 72 interrupts. Don't reset the "route to SP" bit (4).
>
> I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the
> SP-based keyboard for me and defines
>
On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
and 72 interrupts. Don't reset the "route to SP" bit (4).
I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the
SP-based keyboard for me and defines
ICU_INT_ROUTE_SP_IRQ to be 1 << 4. When asked for a data
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