On Fri, Aug 02, 2019 at 06:54:27AM +0300, Daniel Baluta wrote:
> One more thing. See below:
>
> On Wed, Jul 31, 2019 at 12:14 PM Richard Zhu wrote:
>
>
>
> > -/* Control Register */
> > -#define IMX_MU_xCR 0x24
> > /* General Purpose Interrupt Enable */
> > #define IMX_MU_xCR_GIE
One more thing. See below:
On Wed, Jul 31, 2019 at 12:14 PM Richard Zhu wrote:
> -/* Control Register */
> -#define IMX_MU_xCR 0x24
> /* General Purpose Interrupt Enable */
> #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
> /* Receive Interrupt Enable */
> @@ -44,6 +36,13 @@
> -Original Message-
> From: Daniel Baluta
> Sent: 2019年8月1日 22:47
> To: Richard Zhu
> Cc: jassisinghb...@gmail.com; Oleksij Rempel ;
> Aisheng Dong ; Linux Kernel Mailing List
> ; linux-arm-kernel
> ; dl-linux-imx
> Subject: [EXT] Re: [PATCH v3] mailbox: imx
Hi Richard,
Thanks for the patch. Please always add linux-...@nxp.com mailing
list for imx related patches. I missed it.
Few comments inline.
Please also update in a separate patch attached to this series
the devictree bindings doc Documentation/devicetree/bindings/mailbox/fsl,mu.txt
by adding d
There is a version1.0 MU on i.MX7ULP platform.
One new version ID register is added, and it's offset is 0.
TRn registers are defined at the offset 0x20 ~ 0x2C.
RRn registers are defined at the offset 0x40 ~ 0x4C.
SR/CR registers are defined at 0x60/0x64.
Extend this driver to support it.
Signed-of
There is a version1.0 MU on i.MX7ULP platform.
One new version ID register is added, and it's offset is 0.
TRn registers are defined at the offset 0x20 ~ 0x2C.
RRn registers are defined at the offset 0x40 ~ 0x4C.
SR/CR registers are defined at 0x60/0x64.
Extend this driver to support it.
Signed-of
Change logs:
v2 --> v3:
- Format the patch-set refer to Oleksij's guidance.
- Init the register array by a simple way recommended by Oleksij.
- Add Reviewed-by: Oleksij Rempel tag.
v1 --> v2:
- Use to have the register layout linked on probe, suggested by
Oleksij Rempel .
- Add Revie
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