Hi Krzysztof,
On Mon, Sep 21, 2020 at 10:46:45PM +0200, Krzysztof Kozlowski wrote:
> WhOn Mon, 21 Sep 2020 at 22:31, Moritz Fischer wrote:
> >
> > Hi Krzysztof,
> >
> > On Mon, Sep 21, 2020 at 09:23:11AM +0200, Krzysztof Kozlowski wrote:
> > > On Mon, Sep 21, 2020 at 01:31:20PM +0800, Xu Yilun wr
WhOn Mon, 21 Sep 2020 at 22:31, Moritz Fischer wrote:
>
> Hi Krzysztof,
>
> On Mon, Sep 21, 2020 at 09:23:11AM +0200, Krzysztof Kozlowski wrote:
> > On Mon, Sep 21, 2020 at 01:31:20PM +0800, Xu Yilun wrote:
> > > This driver is for the EMIF private feature implemented under FPGA
> > > Device Featu
Hi Krzysztof,
On Mon, Sep 21, 2020 at 09:23:11AM +0200, Krzysztof Kozlowski wrote:
> On Mon, Sep 21, 2020 at 01:31:20PM +0800, Xu Yilun wrote:
> > This driver is for the EMIF private feature implemented under FPGA
> > Device Feature List (DFL) framework. It is used to expose memory
> > interface s
On Mon, Sep 21, 2020 at 01:31:20PM +0800, Xu Yilun wrote:
> This driver is for the EMIF private feature implemented under FPGA
> Device Feature List (DFL) framework. It is used to expose memory
> interface status information as well as memory clearing control.
>
> The purpose of memory clearing bl
This driver is for the EMIF private feature implemented under FPGA
Device Feature List (DFL) framework. It is used to expose memory
interface status information as well as memory clearing control.
The purpose of memory clearing block is to zero out all private memory
when FPGA is to be reprogramme
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