Re: [PATCH v3 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

On Wed, 30 Nov 2016, Joshua Clayton wrote: Hi Joshua, The DT bindings will need Rob Herring's ack. The bitrev.h changes will need Russell King's ack. I've made some comments on patch 3/3 but it looks good to me besides that. Once we have those other acks, please submit your v4 including fixes

[PATCH v3 0/3] Altera Cyclone Passive Serial SPI FPGA Manager

This series adds an FPGA manager for Altera cyclone FPGAs that can program them using an spi port and a couple of gpios, using Alteras passive serial protocol. Changes from v2: - Merged patch 3 and 4 as suggested in review by Moritz Fischer - Changed FPGA_MIN_DELAY from 250 to 50 ms is the time a