Re: [PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-08 Thread Rob Herring
On Mon, Mar 08, 2021 at 11:22:17AM -0700, Rob Herring wrote: > On Mon, Mar 01, 2021 at 04:17:49PM +0100, Benjamin Gaignard wrote: > > The two VPUs inside IMX8MQ share the same control block which can be see > > as a reset hardware block. > > In order to be able to add the second VPU (for HECV decod

Re: [PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-08 Thread Rob Herring
On Mon, Mar 01, 2021 at 04:17:49PM +0100, Benjamin Gaignard wrote: > The two VPUs inside IMX8MQ share the same control block which can be see > as a reset hardware block. > In order to be able to add the second VPU (for HECV decoding) it will be > more handy if the both VPU drivers instance don't h

Re: [PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-05 Thread Benjamin Gaignard
Le 03/03/2021 à 17:25, Philipp Zabel a écrit : On Wed, 2021-03-03 at 16:20 +0100, Benjamin Gaignard wrote: Le 03/03/2021 à 15:17, Philipp Zabel a écrit : Hi Benjamin, On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote: The two VPUs inside IMX8MQ share the same control block which ca

Re: [PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-04 Thread Adam Ford
On Wed, Mar 3, 2021 at 5:24 PM Philipp Zabel wrote: > > On Wed, 2021-03-03 at 16:20 +0100, Benjamin Gaignard wrote: > > Le 03/03/2021 à 15:17, Philipp Zabel a écrit : > > > Hi Benjamin, > > > > > > On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote: > > > > The two VPUs inside IMX8MQ share

Re: [PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-03 Thread Philipp Zabel
On Wed, 2021-03-03 at 16:20 +0100, Benjamin Gaignard wrote: > Le 03/03/2021 à 15:17, Philipp Zabel a écrit : > > Hi Benjamin, > > > > On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote: > > > The two VPUs inside IMX8MQ share the same control block which can be see > > > as a reset hardware

Re: [PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-03 Thread Benjamin Gaignard
Le 03/03/2021 à 15:17, Philipp Zabel a écrit : Hi Benjamin, On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote: The two VPUs inside IMX8MQ share the same control block which can be see as a reset hardware block. This isn't a reset controller though. The control block also contains cl

Re: [PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-03 Thread Philipp Zabel
Hi Benjamin, On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote: > The two VPUs inside IMX8MQ share the same control block which can be see > as a reset hardware block. This isn't a reset controller though. The control block also contains clock gates of some sort and a filter register for

[PATCH v3 0/5] Reset driver for IMX8MQ VPU hardware block

2021-03-01 Thread Benjamin Gaignard
The two VPUs inside IMX8MQ share the same control block which can be see as a reset hardware block. In order to be able to add the second VPU (for HECV decoding) it will be more handy if the both VPU drivers instance don't have to share the control block registers. This lead to implement it as an i