On Tuesday 27 October 2015 11:39 PM, Suzuki K. Poulose wrote:
> I am afraid that would impose a new ABI with complications on how we
> handle information about the CPUs in different states (online, offline,
> etc). I am open to suggestions here.
No I agree it would be non-trivial to maintain this
On Tuesday 27 October 2015 11:39 PM, Suzuki K. Poulose wrote:
> I am afraid that would impose a new ABI with complications on how we
> handle information about the CPUs in different states (online, offline,
> etc). I am open to suggestions here.
No I agree it would be non-trivial to maintain this
On 25/10/15 08:06, Siddhesh Poyarekar wrote:
On Tuesday 13 October 2015 10:52 PM, Suzuki K. Poulose wrote:
Apart from the selected feature registers, we expose MIDR_EL1 (Main
ID Register). The user should be aware that, reading MIDR_EL1 can be
tricky on a heterogeneous system (just like
On 25/10/15 08:06, Siddhesh Poyarekar wrote:
On Tuesday 13 October 2015 10:52 PM, Suzuki K. Poulose wrote:
Apart from the selected feature registers, we expose MIDR_EL1 (Main
ID Register). The user should be aware that, reading MIDR_EL1 can be
tricky on a heterogeneous system (just like
On Tuesday 13 October 2015 10:52 PM, Suzuki K. Poulose wrote:
> Apart from the selected feature registers, we expose MIDR_EL1 (Main
> ID Register). The user should be aware that, reading MIDR_EL1 can be
> tricky on a heterogeneous system (just like getcpu()). We export the
> value of the current
On Tuesday 13 October 2015 10:52 PM, Suzuki K. Poulose wrote:
> Apart from the selected feature registers, we expose MIDR_EL1 (Main
> ID Register). The user should be aware that, reading MIDR_EL1 can be
> tricky on a heterogeneous system (just like getcpu()). We export the
> value of the current
On Fri, Oct 16, 2015 at 04:32:14PM +0100, Suzuki K. Poulose wrote:
> On 16/10/15 16:13, Dave Martin wrote:
> >On Tue, Oct 13, 2015 at 06:22:08PM +0100, Suzuki K. Poulose wrote:
> >>This series introduces a new infrastructure to keep track of the CPU
> >>feature registers on ARMv8-A for arm64
On 16/10/15 16:13, Dave Martin wrote:
On Tue, Oct 13, 2015 at 06:22:08PM +0100, Suzuki K. Poulose wrote:
This series introduces a new infrastructure to keep track of the CPU
feature registers on ARMv8-A for arm64 kernel. It provides the safe value
[...]
Please run checkpatch over the
On Tue, Oct 13, 2015 at 06:22:08PM +0100, Suzuki K. Poulose wrote:
> This series introduces a new infrastructure to keep track of the CPU
> feature registers on ARMv8-A for arm64 kernel. It provides the safe value
[...]
Please run checkpatch over the series...
Cheers
---Dave
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To unsubscribe
On Tue, Oct 13, 2015 at 06:22:08PM +0100, Suzuki K. Poulose wrote:
> This series introduces a new infrastructure to keep track of the CPU
> feature registers on ARMv8-A for arm64 kernel. It provides the safe value
[...]
Please run checkpatch over the series...
Cheers
---Dave
--
To unsubscribe
On 16/10/15 16:13, Dave Martin wrote:
On Tue, Oct 13, 2015 at 06:22:08PM +0100, Suzuki K. Poulose wrote:
This series introduces a new infrastructure to keep track of the CPU
feature registers on ARMv8-A for arm64 kernel. It provides the safe value
[...]
Please run checkpatch over the
On Fri, Oct 16, 2015 at 04:32:14PM +0100, Suzuki K. Poulose wrote:
> On 16/10/15 16:13, Dave Martin wrote:
> >On Tue, Oct 13, 2015 at 06:22:08PM +0100, Suzuki K. Poulose wrote:
> >>This series introduces a new infrastructure to keep track of the CPU
> >>feature registers on ARMv8-A for arm64
This series introduces a new infrastructure to keep track of the CPU
feature registers on ARMv8-A for arm64 kernel. It provides the safe value
of a CPU feature register across all the CPUs on (a heterogeneous) system.
The infrastructure checks the individual CPU feature registers as they are
This series introduces a new infrastructure to keep track of the CPU
feature registers on ARMv8-A for arm64 kernel. It provides the safe value
of a CPU feature register across all the CPUs on (a heterogeneous) system.
The infrastructure checks the individual CPU feature registers as they are
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