[PATCH v3 01/15] clk: tegra: Add binding for the Tegra124 DFLL clocksource

From: Tuomas Tynkkynen The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual Tegra124 clock-and-reset controller, so it gets its own node in the device tree.

[PATCH v3 01/15] clk: tegra: Add binding for the Tegra124 DFLL clocksource

From: Tuomas Tynkkynen ttynkky...@nvidia.com The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual Tegra124 clock-and-reset controller, so it gets its own node in the