[PATCH v3 05/15] clk: tegra: Add DFLL DVCO reset control for Tegra124

From: Paul Walmsley The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP

[PATCH v3 05/15] clk: tegra: Add DFLL DVCO reset control for Tegra124

From: Paul Walmsley pwalms...@nvidia.com The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and