Re: [PATCH v3 06/13] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write

I am not sure I like this approach. For each and every writel (including pio_writes) you will add a few cpu cycles, since you need to check for "mclk_delayed_writes" no matter of variant. How about, adding a new function pointer in the struct mmci_host, for "writel operations" which you co

Re: [PATCH v3 06/13] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write

On 23 May 2014 14:51, wrote: > From: Srinivas Kandagatla > > Most of the Qcomm SD card controller registers must be updated to the MCLK > domain so subsequent writes to registers will be ignored until 3 clock cycles > have passed. > > This patch adds a 3 clock cycle delay required after writing

[PATCH v3 06/13] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write

From: Srinivas Kandagatla Most of the Qcomm SD card controller registers must be updated to the MCLK domain so subsequent writes to registers will be ignored until 3 clock cycles have passed. This patch adds a 3 clock cycle delay required after writing to controller registers on Qualcomm SOCs. W