[PATCH v3 07/14] drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent

On SoCs with two display pipelines, it is possible that the two pipelines are active at the same time, with potentially incompatible dot clocks. Let the HDMI encoder's TMDS clock go through all of its parents when calculating possible clock rates. This allows usage of the second video PLL as its

[PATCH v3 07/14] drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent

On SoCs with two display pipelines, it is possible that the two pipelines are active at the same time, with potentially incompatible dot clocks. Let the HDMI encoder's TMDS clock go through all of its parents when calculating possible clock rates. This allows usage of the second video PLL as its