On Friday 07 September 2012, Catalin Marinas wrote:
> The patch adds support for thread creation and context switching. The
> context switching CPU specific code is introduced with the CPU support
> patch (part of the arch/arm64/mm/proc.S file). AArch64 supports
> ASID-tagged TLBs and the ASID can
The patch adds support for thread creation and context switching. The
context switching CPU specific code is introduced with the CPU support
patch (part of the arch/arm64/mm/proc.S file). AArch64 supports
ASID-tagged TLBs and the ASID can be either 8 or 16-bit wide (detectable
via the ID_AA64AFR0_E
2 matches
Mail list logo