Re: [PATCH v3 09/27] perf parse-events: Create two hybrid cache events

Hi Jiri, On 4/9/2021 9:48 PM, Jiri Olsa wrote: On Mon, Mar 29, 2021 at 03:00:28PM +0800, Jin Yao wrote: SNIP index 1bbd0ba92ba7..3692fa3c964a 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -458,6 +458,7 @@ int parse_events_add_cache(struct list_head *list,

Re: [PATCH v3 09/27] perf parse-events: Create two hybrid cache events

On Mon, Mar 29, 2021 at 03:00:28PM +0800, Jin Yao wrote: SNIP > index 1bbd0ba92ba7..3692fa3c964a 100644 > --- a/tools/perf/util/parse-events.c > +++ b/tools/perf/util/parse-events.c > @@ -458,6 +458,7 @@ int parse_events_add_cache(struct list_head *list, int > *idx, > int cache_type = -1,

[PATCH v3 09/27] perf parse-events: Create two hybrid cache events

For cache events, they have pre-defined configs. The kernel needs to know where the cache event comes from (e.g. from cpu_core pmu or from cpu_atom pmu). But the perf type 'PERF_TYPE_HW_CACHE' can't carry pmu information. So the kernel introduces a new type 'PERF_TYPE_HW_CACHE_PMU'. The new attr.