Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 17:45 GMT+08:00 Guo Ren : > Hello, > > CPU team could improve the tlbop_*. Eg: Design a hardware > internal flag bit for SR_TLB_VPN, tlbop_* will invalid it and mtsr > SR_TLB_VPN will valid it. > > So: > On Wed, Dec 13, 2017 at 05:03:33PM +0800, Greentime Hu wrote: >>

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 17:45 GMT+08:00 Guo Ren : > Hello, > > CPU team could improve the tlbop_*. Eg: Design a hardware > internal flag bit for SR_TLB_VPN, tlbop_* will invalid it and mtsr > SR_TLB_VPN will valid it. > > So: > On Wed, Dec 13, 2017 at 05:03:33PM +0800, Greentime Hu wrote: >> mtsr addr1

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

Hello, CPU team could improve the tlbop_*. Eg: Design a hardware internal flag bit for SR_TLB_VPN, tlbop_* will invalid it and mtsr SR_TLB_VPN will valid it. So: On Wed, Dec 13, 2017 at 05:03:33PM +0800, Greentime Hu wrote: > mtsr addr1 NDS32_SR_TLB_VPN > interrupt coming > mtsr

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

Hello, CPU team could improve the tlbop_*. Eg: Design a hardware internal flag bit for SR_TLB_VPN, tlbop_* will invalid it and mtsr SR_TLB_VPN will valid it. So: On Wed, Dec 13, 2017 at 05:03:33PM +0800, Greentime Hu wrote: > mtsr addr1 NDS32_SR_TLB_VPN > interrupt coming > mtsr

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 16:53 GMT+08:00 Guo Ren : > On Wed, Dec 13, 2017 at 04:30:41PM +0800, Greentime Hu wrote: >> 2017-12-13 16:19 GMT+08:00 Guo Ren : >> > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: >> > >> >> I think it should be fine if an

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 16:53 GMT+08:00 Guo Ren : > On Wed, Dec 13, 2017 at 04:30:41PM +0800, Greentime Hu wrote: >> 2017-12-13 16:19 GMT+08:00 Guo Ren : >> > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: >> > >> >> I think it should be fine if an interruption between mtsr_dsb and >> >>

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

On Wed, Dec 13, 2017 at 04:30:41PM +0800, Greentime Hu wrote: > 2017-12-13 16:19 GMT+08:00 Guo Ren : > > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: > > > >> I think it should be fine if an interruption between mtsr_dsb and > >> tlbop_rwr because this is a

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

On Wed, Dec 13, 2017 at 04:30:41PM +0800, Greentime Hu wrote: > 2017-12-13 16:19 GMT+08:00 Guo Ren : > > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: > > > >> I think it should be fine if an interruption between mtsr_dsb and > >> tlbop_rwr because this is a optimization by sw. > >

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 16:19 GMT+08:00 Guo Ren : > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: > >> I think it should be fine if an interruption between mtsr_dsb and >> tlbop_rwr because this is a optimization by sw. > > Fine? When there is an unexpected vaddr in

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 16:19 GMT+08:00 Guo Ren : > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: > >> I think it should be fine if an interruption between mtsr_dsb and >> tlbop_rwr because this is a optimization by sw. > > Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte)

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: > I think it should be fine if an interruption between mtsr_dsb and > tlbop_rwr because this is a optimization by sw. Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will break that vaddr's pfn in the CPU

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: > I think it should be fine if an interruption between mtsr_dsb and > tlbop_rwr because this is a optimization by sw. Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will break that vaddr's pfn in the CPU

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 10:16 GMT+08:00 Guo Ren : > On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote: >> From: Greentime Hu > [...] >> diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c > [...] >> +#ifndef CONFIG_CPU_CACHE_ALIASING >>

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

2017-12-13 10:16 GMT+08:00 Guo Ren : > On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote: >> From: Greentime Hu > [...] >> diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c > [...] >> +#ifndef CONFIG_CPU_CACHE_ALIASING >> +void update_mmu_cache(struct

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote: > From: Greentime Hu [...] > diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c [...] > +#ifndef CONFIG_CPU_CACHE_ALIASING > +void update_mmu_cache(struct vm_area_struct *vma, unsigned long

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote: > From: Greentime Hu [...] > diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c [...] > +#ifndef CONFIG_CPU_CACHE_ALIASING > +void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, > +

[PATCH v3 09/33] nds32: Cache and TLB routines

From: Greentime Hu This patch contains cache and TLB maintenance functions. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/nds32/include/asm/cache.h | 25 ++

[PATCH v3 09/33] nds32: Cache and TLB routines

From: Greentime Hu This patch contains cache and TLB maintenance functions. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/nds32/include/asm/cache.h | 25 ++ arch/nds32/include/asm/cache_info.h| 26 ++ arch/nds32/include/asm/cacheflush.h| 57