Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support

On Tue, Apr 17, 2018 at 1:38 AM, Alan Kao wrote: > +static inline void write_counter(int idx, u64 value) > +{ > + /* currently not supported */ > +} CSR writes can be emulated: https://github.com/riscv/riscv-pk/pull/98 Or at least write_counter() should have BUG() or WARN_ONCE() or someth

Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support

This does not compile: /freedom-u-sdk/linux/arch/riscv/kernel/perf_event.c: In function 'riscv_pmu_stop': /freedom-u-sdk/linux/arch/riscv/kernel/perf_event.c:258:12: error: 'const struct riscv_pmu' has no member named 'read' riscv_pmu->read(event); ^~ /freedom-u-sdk/linux/arch/riscv

[PATCH v3 1/2] perf: riscv: preliminary RISC-V support

This patch provide a basic PMU, riscv_base_pmu, which supports two general hardware event, instructions and cycles. Furthermore, this PMU serves as a reference implementation to ease the portings in the future. riscv_base_pmu should be able to run on any RISC-V machine that conforms to the Priv-S