anuragku...@gmail.com; linux-kernel@vger.kernel.org; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org
>Subject: Re: [PATCH v3 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy
>core
>
>Hi Anurag,
>
>On Wed, Sep 5, 2018 at 10:14 PM Anurag Kumar Vulis
Hi Anurag,
On Wed, Sep 5, 2018 at 10:14 PM Anurag Kumar Vulisha
wrote:
>
> ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
> peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
> rely on any of the four GT lanes for PHY layer. This patch adds driver
>
Hi Rob,
Thanks a lot for spending your time in reviewing this patch series,
>> Signed-off-by: Anurag Kumar Vulisha
>> ---
>> Changes in v3:
>> 1. Corrected the Documentation as suggested by Vivek Gautam
>>
>> Changes in v2:
>> 1. Fixed the compilation error when compiled phy-zynqmp.
On Wed, Sep 05, 2018 at 10:12:26PM +0530, Anurag Kumar Vulisha wrote:
> ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
> peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
> rely on any of the four GT lanes for PHY layer. This patch adds driver
> for
ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
rely on any of the four GT lanes for PHY layer. This patch adds driver
for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha
---
Changes in v3:
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