On Wed, Aug 29, 2018 at 9:40 AM Linus Walleij wrote:
> This patch applied for fixes with Doug and Bjorn's ACKs.
>
> I suppose you will respin the two others and obtain buy-in from
> the same people for these.
Scrap that. I saw Bjorn has ACKed the two others so applied them for
next (v4.20).
On Wed, Aug 29, 2018 at 9:40 AM Linus Walleij wrote:
> This patch applied for fixes with Doug and Bjorn's ACKs.
>
> I suppose you will respin the two others and obtain buy-in from
> the same people for these.
Scrap that. I saw Bjorn has ACKed the two others so applied them for
next (v4.20).
On Thu, Aug 16, 2018 at 10:06 PM Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw" status
On Thu, Aug 16, 2018 at 10:06 PM Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw" status
On Thu 16 Aug 13:06 PDT 2018, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw" status
On Thu 16 Aug 13:06 PDT 2018, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw" status
On Thu, Aug 16, 2018 at 10:49 PM Doug Anderson wrote:
> On Thu, Aug 16, 2018 at 1:06 PM, Stephen Boyd wrote:
> > The interrupt controller hardware in this pin controller has two status
> > enable bits. The first "normal" status enable bit enables or disables
> > the summary interrupt line being
On Thu, Aug 16, 2018 at 10:49 PM Doug Anderson wrote:
> On Thu, Aug 16, 2018 at 1:06 PM, Stephen Boyd wrote:
> > The interrupt controller hardware in this pin controller has two status
> > enable bits. The first "normal" status enable bit enables or disables
> > the summary interrupt line being
Hi,
On Thu, Aug 16, 2018 at 1:06 PM, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw"
Hi,
On Thu, Aug 16, 2018 at 1:06 PM, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw"
The interrupt controller hardware in this pin controller has two status
enable bits. The first "normal" status enable bit enables or disables
the summary interrupt line being raised when a gpio interrupt triggers
and the "raw" status enable bit allows or prevents the hardware from
latching an
The interrupt controller hardware in this pin controller has two status
enable bits. The first "normal" status enable bit enables or disables
the summary interrupt line being raised when a gpio interrupt triggers
and the "raw" status enable bit allows or prevents the hardware from
latching an
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