Add support for reading the source clock from snd_soc_params_to_bclk
so the machine driver is not required to call cs42l42_set_sysclk

Signed-off-by: Lucas Tanure <tanur...@opensource.cirrus.com>
---
Changes in v3:
- No changes

Changes in v2:
- No changes

 sound/soc/codecs/cs42l42.c | 17 +++++++++++++----
 sound/soc/codecs/cs42l42.h |  1 +
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 594bf22521037..68b7ed71ad542 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -588,10 +588,16 @@ static int cs42l42_pll_config(struct snd_soc_component 
*component)
 {
        struct cs42l42_private *cs42l42 = 
snd_soc_component_get_drvdata(component);
        int i;
+       u32 clk;
        u32 fsync;
 
+       if (!cs42l42->sclk)
+               clk = cs42l42->bclk;
+       else
+               clk = cs42l42->sclk;
+
        for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
-               if (pll_ratio_table[i].sclk == cs42l42->sclk) {
+               if (pll_ratio_table[i].sclk == clk) {
                        /* Configure the internal sample rate */
                        snd_soc_component_update_bits(component, 
CS42L42_MCLK_CTL,
                                        CS42L42_INTERNAL_FS_MASK,
@@ -611,12 +617,12 @@ static int cs42l42_pll_config(struct snd_soc_component 
*component)
                                        (pll_ratio_table[i].mclk_div <<
                                        CS42L42_MCLKDIV_SHIFT));
                        /* Set up the LRCLK */
-                       fsync = cs42l42->sclk / cs42l42->srate;
-                       if (((fsync * cs42l42->srate) != cs42l42->sclk)
+                       fsync = clk / cs42l42->srate;
+                       if (((fsync * cs42l42->srate) != clk)
                                || ((fsync % 2) != 0)) {
                                dev_err(component->dev,
                                        "Unsupported sclk %d/sample rate %d\n",
-                                       cs42l42->sclk,
+                                       clk,
                                        cs42l42->srate);
                                return -EINVAL;
                        }
@@ -788,6 +794,7 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream 
*substream,
        unsigned int val = 0;
 
        cs42l42->srate = params_rate(params);
+       cs42l42->bclk = snd_soc_params_to_bclk(params);
 
        switch(substream->stream) {
        case SNDRV_PCM_STREAM_CAPTURE:
@@ -921,6 +928,8 @@ static struct snd_soc_dai_driver cs42l42_dai = {
                        .rates = SNDRV_PCM_RATE_8000_192000,
                        .formats = CS42L42_FORMATS,
                },
+               .symmetric_rate = 1,
+               .symmetric_sample_bits = 1,
                .ops = &cs42l42_ops,
 };
 
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h
index e12828877a20d..429c6833fc811 100644
--- a/sound/soc/codecs/cs42l42.h
+++ b/sound/soc/codecs/cs42l42.h
@@ -771,6 +771,7 @@ struct  cs42l42_private {
        struct gpio_desc *reset_gpio;
        struct completion pdn_done;
        struct snd_soc_jack jack;
+       int bclk;
        u32 sclk;
        u32 srate;
        u8 plug_state;
-- 
2.30.1

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