On 5/1/2015 11:12 PM, Jim Lin wrote:
>
>> +static void clk_plle_tegra210_is_enabled(struct struct clk_hw *hw) {
> Returned type is "int" instead of "void".
> Also one "struct" only for "clk_hw *hw"?
>
>> +struct tegra_clk_pll *pll = to_clk_pll(hw);
>> +u32 val;
>> +
>> +val = pll_read
> +static void clk_plle_tegra210_is_enabled(struct struct clk_hw *hw) {
Returned type is "int" instead of "void".
Also one "struct" only for "clk_hw *hw"?
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val;
> +
> + val = pll_readl_base(pll);
> +
> + return val & PLLE_BASE
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registeration functions specific
to Tegra210 which will handle them appropriately.
Signed-off-by: Rhyland Klein
---
v2:
- Fixed plle logic. PLLE on Tegra210 has had its enable bit m
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